make - Maintains program dependencies
make [-C | -c] [-eiNnqrstx] [-p | -Tp] [-k | -s] [-U |
-u] [-f makefile]... [macro=value...] [target...]
Does not try to find a corresponding RCS file and check it
out if the file does not exist. Tries to find a corresponding
Revision Control System (RCS) file and check it
out if the file does not exist. The option is on by
default. The -C and -coptions are mutually exclusive.
Specifies that environmental variables override macro
assignments within makefiles. Ignores nonzero exit of
shell commands in the makefile. Equivalent to specifying
- (dash) before each command line in the makefile. Continues
processing after errors are encountered, but only
on those targets that do not depend on the target whose
creation caused the error. If an error is encountered,
make exits with a status greater than or equal to 1. The
-k and -S options are mutually exclusive. Displays the
commands that would have been executed, but does not actually
execute them. If the lines have + (plus sign) prefixes,
the commands will be executed. [Tru64 UNIX] Disables
all Makeconf processing. Displays all the macro
definitions target and prerequisite descriptions including
modification times. This information is displayed both
before and after description file processing has occurred.
Does not execute any commands, but returns exit value 0
(zero) if the specified targets are up-to-date and 1, otherwise.
If the lines have + (plus sign) prefixes, the
commands will be executed. Does not use the built-in
rules specified in the system makefile. Does not echo any
commands as they are executed. Equivalent to specifying @
before each command line in the makefile. Terminates make
process if errors are encountered during updates. This is
the default behavior and is the opposite of the -k option.
The -Sand -koptions are mutually exclusive. Creates a
target or updates its modification time to make it appear
up-to-date, instead of rebuilding a target as specified in
the makefile. The target command lines are typically not
executed, unless the target command lines have + (plus
sign) prefixes, in which case they are executed. [Tru64
UNIX] This option must be used with -p option to echo
target descriptions and to suppress macro definitions,
global variables, environment variables, suffix information,
and suffix transformation rules. If -p is not indicated
with this option no action will be taken. [Tru64
UNIX] Does not unlink files that were previously checked
out by RCS. This is the opposite of the -U option, which
is the default. [Tru64 UNIX] Unlinks files that were
previously checked out by RCS. This option is set as the
default. If the pseudotarget is defined in the dependency
file, the target files are not removed. The -U and -u are
mutually exclusive. [Tru64 UNIX] Does not execute any
commands. Performs RCS checkout on target files if the -C
option is also specified, which is the default. The files
will not be unlinked if the -u option is also specified.
This option is useful for creating working copies of
source files. When used with another option, the -x option
performs only the action specified by that option without
performing any actions specified in the current makefile.
Specifies a makefile to read instead of the default makefile.
If makefile is - (dash), standard input is read.
If you specify multiple makefiles, they are read in the
order entered. Sets the macro or variable to value. You
may specify multiple macro=value pairs. Specifies the
target or targets to update or create. If unspecified, the
first target contained within the description file is
selected.
[Tru64 UNIX] The make(1p) command is one of several versions
available. See the SEE ALSO section for references
to information about other versions of the command. By
default, the make(1) command is invoked if you type the
command name with no path. To access the enhanced
XPG4/POSIX compliant make(1p) version described in this
reference page, use the following command path:
/usr/bin/posix/make
[Tru64 UNIX] Note that this version of make is optional
and might not be installed on your system.
The make command is designed to simplify the maintenance
of other programs. The make command can update or create
a file or program (target) based on whether the program
dependencies (prerequisites) have been modified relative
to the time of last modification of the program itself.
The make command's input is a description file (makefile)
containing a list of specifications. The specifications
define the relationship between target and prerequisite.
The specification also contains the commands to create or
update a target. By default, the following description
files are tried in sequence to provide this list of specifications:
SCCS/s.Makefile.
There are four different types of lines in a makefile:
file dependency lines, shell commands, variable assignments,
and comments. File dependency lines and optional
shell commands define file dependency specifications.
In general, lines may be continued from one line to the
next by ending them with a \ (backslash). The trailing
newline character and initial white space on the following
line are compressed into a single space. Comment lines
inserted between lines that have been continued are
ignored.
File Dependency Specifications [Toc] [Back]
Dependency lines consist of one or more targets, an operator,
zero or more sources (prerequisites), and an optional
command. This creates a relationship where the targets
depend on the sources and are usually created from them.
The exact relationship between the target and the source
is determined by the operator that separates them. The
operators are as follows: A target is considered out-ofdate
if its modification time is less than those of any of
its sources. Sources for a target accumulate over dependency
lines when this operator is used. The target is
removed if make is interrupted unless the target has the
attribute. If no sources are specified, the target is
always re-created. Otherwise, a target is considered outof-date
if any of its sources were modified more recently
than the target. Sources for a target do not accumulate
over dependency lines when this operator is used. The
target will not be removed if make is interrupted. Targets
are always recreated, but not until all sources have
been examined and recreated as necessary. Sources for a
target accumulate over dependency lines when this operator
is used. The target is removed if make is interrupted.
The SYNTAX is: target ! dep1 dep2 ... depn.
File dependency specifications have two types of rules,
inference and target, as follows: Have one target with no
/ (slash) and a minimum of one (period). These rules
specify how a target is to be made up-to-date. Can have
more than one target. These rules specify how to build
the target.
Makefile Execution [Toc] [Back]
The make command executes the commands in the makefile
line by line. As make executes each command, it writes
the command to standard output (unless otherwise directed,
for example the -s option). A makefile must have a tab in
front of the commands on each line.
When a command is executed through make, it uses make's
execution environment. This includes any macros from the
command line to make, and any environment variables specified
in the MAKEFLAGS variable (refer to Variable Assignments).
The make command's environment variables overwrite
any variables of the same name in the existing environment.
Target Rules [Toc] [Back]
Target rules have the following format:
target [target...] :[:] [prerequisite...] [;command]
<Tab>command . . .
Multiple targets and prerequisites are separated by spaces
(note that the list of prerequisites can be empty). Any
text that follows the ; (semicolon) and all of the subsequent
lines that begin with a tab character are considered
commands to be used to update the target. A new target
entry is started when a new line does not begin with a tab
character or # (number sign). The following section lists
the special sources, or prerequisites, and targets for a
makefile.
When sources are listed on the dependency line, make
treats each source as a dependency of the target. Each
source then in turn becomes a target. The make command
assumes the file is located in the current directory.
If the target does not have a makefile entry, or the
dependency specification for the target does not contain a
command or rule, make attempts to derive a command/rule in
the following order: First, make attempts to derive a command/rule
from make's default inference or transformation
rules. Second, make attempts to apply the commands associated
with the SCCS_GET special target to derive a command
to locate files not found in the current directory.
Third, make attempts to apply the commands associated with
the DEFAULT special target to derive a command to create a
target when no other rule applies.
When make target is called with a valid POSIX
makefile, that is, with defined, and target is not
up to date, and the target rule contains no associated
commands, and make cannot derive a command or
rule, then make writes a message to standard output
indicating that no action was taken. For example,
consider the following makefile:
POSIX: target.U1: target.U2: target.U3 target.U3:
Running make with this makefile produces the following
result: $ make target.U1 Warning! No action
taken on target.U1. $ make target.U2 Warning! No
action taken on target.U3 Warning! No action taken
on target.U2.
If the special target is not specified in the example
above, the result would be as follows: $ make
target.U1 $ $ make target.U2 $
RCS Support [Toc] [Back]
Make Behavior For RCS Target
When a file is specified on the dependency line and it is
not present in the current directory, make will search for
it. The search path starts in the current directory, then
the VPATH macro components are searched. If the file does
not exist then RCS version of the file with the suffix ,v
is searched. The search path starts in the current directory,
the VPATH macro components, and the VPATH macro components
with extension /RCS are searched. If an RCS file
is found, it is checked out using the -q option, used for
whatever purpose is required and then deleted.
RCS Builtin Macros [Toc] [Back]
The followings are builtin macros for Revision Control
System(RCS) functionality: CO = co
COFLAGS = -q
RCS Default Rules [Toc] [Back]
The following are the default rules for RCS functionality:
RCS Rule For Non-Defined Suffixes. The following rule will
be used to build a target with a suffix which is
not defined as a prerequisite of target: ,v:
$(CO) $(COFLAGS) $< $@
RCS Rule For Defined Suffixes. The following rule will be
used to build a target with a suffix which is already
defined as a prerequisite of.SUFFIXES target: ,v.c ,v.C
,v.cxx ,v.cc ,v.o ,v.f ,v.f90 ,v.l ,v.y ,v.s:
$(CO) $(COFLAGS) $< $@
Special Targets [Toc] [Back]
Special targets may not be included with other targets;
that is, they must be the only target specified. These
control the operation of the make command. All command
lines associated with this special target are invoked for
any prerequisite that is not a target; that is, no
description file entry for the prerequisite exists or no
other suffix rule can be applied.
The $< (left angle bracket) variable of a target
that inherits the commands for is set to the target's
own name. For example, consider the following
makefile entry:
.POSIX: .DEFAULT:
@echo default = $< target.U: missing
@echo main target = $@
When make is run with this file, the results are as
follows: $ make target.U default = missing main
target = target.U $ make notthere1 notthere2
default = notthere1 default = notthere2 Prerequisites
of this target are targets themselves; this
causes errors from commands associated with them to
be ignored. If no prerequisites are specified, this
is the equivalent of specifying the -i option.
When specified, this keyword enables POSIX make
behavior and disables selected non-POSIX functionality.
This must be the first non-command line of
a makefile. Use this in your makefile if you want
to avoid portability conflicts. Prerequisites of
this target are targets themselves. The special
target prevents the current target from being
removed. If no sources are specified, the attribute
is applied to every target in the file. Normally,
when make is interrupted (for example, with SIGHUP,
SIGTERM, SIGINT, or SIGQUIT), it removes any partially
made targets. If make was invoked with the
-n, -p, or -q options, however, the target is considered
to have the attribute. This special target
defines the commands to retrieve all files not
found in the current directory. By default, the
make command assumes all targets are located in the
current directory. When the target dependency
specification has no sources, but a local targetfile
is present in the current directory, make
assumes the local targetfile is up-to-date. When
this special target is enabled, make attempts to
locate a file named SCCS/s.targetfile. If the
local targetfile exists, make checks to be sure
that the targetfile is up-to-date with respect to
SCCS/s.targetfile. If the local targetfile is
missing, or if the SCCS/s.targetfile is newer, make
automatically issues the commands associated with
this special target to retrieve the most recent
version. If the local targetfile is writable by
anyone, make does not retrieve the latest version.
If an s.file exists in both the current directory
and an SCCS subdirectory, the s.file in the current
directory is used. The s.file in the SCCS subdirectory
is ignored. This special target must be
specified without prerequisites. If this special
target is included in a user makefile, the commands
specified replace this special target's default
command. The default command defined in
/usr/share/mk/posix.mk is as follows:
.SCCS_GET:
sccs $(SCCSFLAGS) get $(SCCSGETFLAGS) $@
This functionality is enabled only if the first
noncomment line of the first makefile read by make
is the target.
To nullify the commands of this special target,
specify this special target in a user makefile
without prerequisites and without commands. Prerequisites
of the target are targets themselves;
this causes commands associated with the target to
not be written to standard output before they are
executed. If no sources are specified, the
attribute is applied to every command in the file.
Prerequisites of the target are appended to the
list of known suffixes. If no suffixes are specified,
any previously specified suffixes are
deleted. These suffixes are used by inference
rules. To change the order of suffixes, you need
to specify an empty entry, then a new list of
entries. Makefiles must not associate commands
with If a target named exists in the description
file, make will attempt to build this target first
automatically before attempting any other target.
If a target named exists in the description file,
make will attempt to build this target automatically
when everything else has been created with no
errors. If a target named exists in the description
file and make is interrupted, the commands in
the script for this target will be executed. If a
target named exists in the description file and no
target is supplied in the command line when make is
invoked, it will take the sources of this target as
the target to create. If no sources are specified
in this target, make will take the first target to
create. Make will treat the sources of this target
as directories in which to search for files it can
not find in the current working directory. If no
sources are given, it will clear out any directories
previously added to the search path. The
search will then take place from the current working
directory i.e. after changing directory to the
object directory. The directory change occurs when
make is finished reading the Makeconf file. The
search order would be: current working directory,
sources of this target and the VPATH macro. This
does a similar thing to it does only files with
already defined suffix.
Target Attribute [Toc] [Back]
In make, files can have attributes. These attributes cause
make to treat the targets in special ways. An attribute is
a special word given as a source to a target on a dependency
line. Name of target attribute may not used as a
main target to create. SYNTAX: target1 ... targetn
:[:][!] dep1 dep2 ... ATTRIBUTE ... depn
Also a line of the form SYNTAX: ATTRIBUTE: target1 ...
targetn
If this attribute is used for a target, that target turns
into make's equivalent of macro. When the target is used
as a source for another target, the other target acquires
the commands, sources and attributes (except targets commands
are added to the end. If more than one marked source
is given to a target, the rules are applied sequentially.
If a attribute named exists in the description file, then
the dependencies of this attribute are considered to be
out-of-date. The dependencies of this attribute are called
phony targets. So make will build each phony target
unconditionally, regardless of whether a file with that
name exists or what its last modification time is. Since
it knows that phony targets do not name actual files that
could be remade from other commands or files, make skips
the implicit rule search for phony targets. This is why
declaring a target phony is good for performance, even
if users are not worried about the actual file existing.
Phony targets may or may not have dependency. If a target
is marked with this attribute and make cannot figure out
how to create it, it will ignore this fact and assume the
file is not really needed or actually exists and make just
cannot find it. This attribute also prevents make from
attempting to touch the target if it is given the -t
option. If a target is not specified to the make command
in any other way, then make will take the first target on
the first dependency line of a makefile as the target to
create. Giving a target this attribute keeps it from this
fate. Special targets and attributes name are also
implicitly marked as
Inference Rules [Toc] [Back]
The make command has a default set of inference rules,
which you can supplement, or overwrite, with additional
inference rule definitions in your makefile. Inference
rules consist of target suffixes and commands. From the
suffixes, make infers the prerequisites, and from both the
suffixes and their prerequisites, make can infer how to
make a target up-to-date. Inference rules have the following
format: rule: <Tab>command . . .
where rule has one of the following forms: A single-suffix
inference rule. This describes how to build a target that
is appended with a single suffix. A double-suffix inference
rule. Also referred to as a transformation rule,
describes how to transform a file with an suffix into a
file with an suffix. The file with the V.s1 suffix can be
thought of as the prerequisite that is transformed into
the target with an suffix.
The s1 and s2 suffixes are defined as prerequisites of the
special target, are specified in when a new line does not
begin with a <Tab> or # (number sign).
If rule is empty, for example:
rule:
execution has no effect, and make will recognize that the
suffix exists, but take no actions when targets are outof-date.
A ~ (tilde) in the preceding rules refers to an SCCS file.
Thus, the rule would transform an SCCS C-language source
file into an object file (.o). Because the s. of the
SCCS files is a prefix, it is incompatible with make's
suffix point of view. Hence, the ~ (tilde) is a way of
changing any file reference into an SCCS file reference.
Restrictions on .o and other single suffix rule
If a target name is a prefix of any of it's prerequisites
whose suffixes are then the default rule will attempt to
create the target if the user does not supply the rule or
command in the makefile for that target. The following is
sample lines from a makefile:
f1: f1.o f2.o f2: f1.o f2.o
Here the default rule will attempt to create an executable
file named f1 or f2 from f1.o and f2.o. The user must
supply the command in makefile for other single suffix
rules if there is more than one prerequisite and there are
interdependencies.
If the target name is not a prefix of any of it's prerequisites
and the prerequisites are interdependent than the
user must supply the rules and commands for that target to
create the target. If the user does not want to create the
target which is not a prefix of its prerequisites then the
user does not have to supply the rules or commands.
If the user does supply a rule in the makefile and the
target name is a prefix of any one of it's prerequisites
then dependency information for the -p and -T options is
not specified. To display the correct dependency information
with -p and -T option do not use the target name
which is a prefix of any of it's prerequisites. To create
target name the user must supply commands in the makefile
for the target.
Libraries [Toc] [Back]
A target or prerequisite may also be a member of an
archive library, and is treated as such if there are
parentheses in the name. For example, library(name.o)
indicates that name is a member of the archive library
library. To update a member of a library from a particular
file, you can use the format suffix is used to update
a member of the archive library. The refers to an archive
library. The member name must be appended with the suffix.
The expression library(name1.o name2.o...) is
invalid.
Using Macros [Toc] [Back]
In makefiles, macro definitions are defined in the format:
variable=value
Macros can appear throughout the makefile, as follows: If
a macro appears in a target line, then it is evaluated
when the target line is read. If a macro appears in a
command line, then it is evaluated when the command is
executed. If a macro appears in a macro definition line,
it is evaluated when the new macro itself appears in a
rule or command.
If a macro has no definition, it evaluates to NULL. A new
macro definition overwrites an existing macro of the same
name. Macros assignments can come from the following, in
the listed order: Default inference rules Contents of the
environment makefiles Command lines
Note, however, that the -e option causes environment variables
to override those defined in the makefile.
Referencing Macros [Toc] [Back]
Macro definitions are referenced as $(MACRO) or ${MACRO}.
If the macro name is a single byte, the ( ) (parentheses)
or { } (braces) can be omitted, but the $ (dollar sign)
must remain.
Generic Macro [Toc] [Back]
Macro Location Substituition
The location parameter specifies what portion of the word
is to be replaced with string. The following characters
have special meaning to location: ^, *, &, and $. The syntax
is as follows: $(MACRO/location/string)
The string parameter is inserted at the beginning of each
word. The string parameter is inserted at the end of each
word. Each word is replaced with the string parameter,
and then the original word is substituted for each occurance
of & (ampersand) in the string parameter.
Macro Set [Toc] [Back]
Appending Macro
The syntax for appending macro definitions is as follows:
SYNTAX:MACRO+=value
Appends the value to the current value of the macro. Words
can be appended to macro values as follows:
MACRO += XX YY ZZ
If MACRO is defined before above statement as MACRO=AA
then the value of $(MACRO) will be : AA XX YY ZZ. If the
MACRO is not defined before the above statement then the
value will be : XX YY ZZ. Otherwise assignment will occur
according to POSIX standard.
Conditional Macro [Toc] [Back]
Assigns the value to the variable if it is not already
defined. The syntax for conditonal macro definitions is as
follows: SYNTAX:MACRO?= value
Value Expanded Macro [Toc] [Back]
Assigns with expansion; that is, expands the value before
assigning it to the macro or variable. Normally, expansion
is not done until the variable is referenced. The syntax
for expanded macro definitions is as follows: SYNTAX:MACRO:=
value
Shell-Command Macro [Toc] [Back]
If there is any reference of variable in shell_commands_script,
expands it, passes it to /bin/sh for execution,
and assigns the result to the variable. Any newlines
in the result are replaced with spaces. The syntax for
expanded macro definitions is as follows: SYNTAX:MACRO!=
shell_commands_script
Variable Name Expansion [Toc] [Back]
Support to evaluate the LHS of variable assignment before
value assignment occurs: MACRO= macro_name
$(MACRO)= value
Make will evaluate $(MACRO) and assign value to the value
of MACRO which is macro_name. In other words make will not
treat $(MACRO) as a variable or macro name. i.e. Variable
MACRO has to be a predefined macro for such macro assignment.
If the definition of MACRO takes place after the
definition of $(MACRO) = value then the macro assignment
to $(MACRO) = value will not be in effect for the later
MACRO definition.
Single Quote Evaluation [Toc] [Back]
Parse a dependency line for single quote and evaluate
shell command(s) inside the single quotes to get the full
dependency list.
The syntax for single quote evaluation is as follows: SYNTAX:target
:[:] targ_1 targ_2 `shell_script arg1 arg2 ...`
targ_m `shell_script arg_1 arg_2 ...\`shell_script ar1
ar2 ...\` arg_n ...` targ_n
Special Macros [Toc] [Back]
The make utility provides features to manipulate, define
and reference macros.
SOURCEDIR and OBJECTDIR Macros [Toc] [Back]
SOURCEDIR macro can be defined in Makeconf file and (or)
in command line to be treated as source root. The syntax
for SOURCEDIR is as follows: SYNTAX:SOURCEDIR=dir1:dir1/src:dir2/src
OBJECTDIR macro can be defined in Makeconf file and (or)
in command line to be treated as object root. The value of
this macro may not contain any colon i.e. only one path is
allowed. The syntax for OBJECTDIR is as follows: SYNTAX:OBJECTDIR==dir1/obj
If OBJECTDIR or SOURCEDIR macro is defined then VPATH
macro will be modified so that make can find target source
files. Path order of VPATH macro are described in . If -N
option is specified then these two macros have no special
effect.
Macro Substring Substitution [Toc] [Back]
A facility is provided to substitute portions of a predefined
macro definition during macro evaluation. The syntax
of this is as follows: $(MACRO:substring1=substring2)
When MACRO is evaluated, all occurrences of substring1
defined in MACRO are substituted with substring2. MACRO
is considered to be made up of a string of characters
optionally separated by spaces or tabs. The substring1 to
be replaced is recognized as a word within MACRO only when
it is delimited by trailing spaces, tabs or a new line.
For example:
MACRO = hello.123 goodbye.123 test:
@echo $(MACRO:123=456)
The previous example yields the following output:
hello.456 goodbye.456
Macro Nesting [Toc] [Back]
Macro nesting is permissible to a maximum of two levels.
This behavior occurs only if the first noncomment line of
the first makefile read by make is not the target; otherwise,
a syntax error occurs. The syntax for nested macro
definitions is as follows: RESULT1=$($(MACRO))
RESULT2=$(ABC$(MACRO)DEF)
The inner and outer macros combine to return the resulting
variable. Nested macros can be used where simple macros
are used. The inner nested macro must not evaluate to
null.
Conditional Macro Definition [Toc] [Back]
Conditional macro definitions are also available; the syntax
is as follows: $(MACRO?string1:string2)
In this macro definition, if MACRO is defined, string1 is
assigned to MACRO; otherwise, the value of string2 is
assigned to MACRO. This behavior occurs only if the first
noncomment line of the first makefile read by make is not
the target; otherwise, a syntax error occurs.
MACRO, string1 or string2 can contain various combinations
of macros. Single or multiple macros and nested macro
combinations are valid. For example:
RESULT1 = $(MACRO?$(STRING1):$(string2)) RESULT2 =
$(MACRO?$(STRING1):$(string2)$(string2))
$($(MACRO)?$(HARDWARE_$(PLATFORM)):$($(PLATFORM)_OS_VERSION))
Configuration Macros [Toc] [Back]
Support for internally defined macros MAKETOP, MAKEDIR,
MAKEPSD, MAKECWD,
These macros are assigned internally. They depend on
VPATH, Makeconf, SOURCEDIR and OBJECTDIR. The relative
path from the starting directory to the Makeconf directory.
The path from the Makeconf directory to the starting
directory. The current directory for make. The path
from the current working i.e. object directory for make to
the starting directory. Absolute path of the starting
i.e. invocation directory of make. Absolute path of the
current working i.e. object directory.
SHELL Macro [Toc] [Back]
The SHELL global macro is special. By default, make sets
SHELL to the path name of the shell command interpreter
(/bin/sh). You can override this default global setting
by redefining SHELL in the makefile or on the command
line. Note that this global macro does not affect, and is
not affected by, the SHELL environment variable.
When make is called with a valid POSIX makefile, that is,
with defined, the SHELL macro has no effect on the shell
that make invokes. By default, the make command uses
/bin/sh to invoke commands. This design is to ensure
portability and to avoid potential conflicts with the user
environment.
If the special target is not specified, you can change the
shell that make invokes by setting the SHELL global macro
to any one of the following: /usr/bin/sh /usr/bin/ksh
/usr/bin/csh /bin/csh /bin/ksh /sbin/sh
[Tru64 UNIX] Alternatively, you can use the SHELL environmental
variable to define which shell make uses by
specifying the -e option on the command line.
Note
This feature is supported for backward compatibility with
other implementations of make but is not recommended for
portability reasons. The recommended method for executing
Non-Bourne shell commands is to create a separate script
file containing those commands and invoke that file from
within the make description file.
Shell Commands [Toc] [Back]
Each target may have associated with it a series of shell
commands, normally used to create the target. Each of the
commands in this script must be preceded by a tab. While
any target may appear on a dependency line, only one of
these dependencies may be followed by a creation script,
unless the :: operator is used.
If the first or first two characters of the command line
are @ and/or - and/or +, the command is treated specially,
as follows: Causes the command not to be echoed before it
is executed. Causes any nonzero exit status of the command
line to be ignored. Causes a command line to be executed,
even though the options -n, -q, or -t are specified.
Variable Assignments [Toc] [Back]
Variables in make are much like variables in the shell,
and, by tradition, consist of all uppercase letters. The
= operator assigns values to variables. Any previous
variable is then overridden.
Any white space before the assigned value is removed; if
the value is being appended, a single space is inserted
between the previous contents of the variable and the
appended value.
Variables are expanded by surrounding the variable name
with either {} (braces) or () (parentheses) and preceding
it with a $ (dollar sign). If the variable name contains
only a single letter, the surrounding braces or parentheses
are not required. This shorter form is not recommended.
Variable substitution occurs at two distinct times,
depending on where the variable is being used. Variables
in dependency lines are expanded as the line is read.
Variables in shell commands are expanded when the shell
command is executed.
The four different classes of variables (in order of
increasing precedence) are as follows: Variables defined
as part of make's environment. Variables defined in the
makefile or in included makefiles. Variables defined as
part of the command line. Variables that are defined specific
to a certain target. The local variables are as follows:
The list of all sources for this target; also known
as >. This local variable may be used in sources on dependency
lines, because it expands to the proper value for
each target on the line. The name of archive file; also
known as!. The name/path of the source from which the
target is to be transformed (the implied source); also
known as <. This local variable may be used only in suffix
rules. The name of the archive member; also known as %.
This local variable may be used in sources or dependency
lines, because it expands to the proper value for each
target on the line. The list of sources for this target
that were deemed out-of-date; also known as ?. This local
variable may be not used in suffix rules. This local
variable evaluates to the current target name with its
suffix deleted. If the target has preceding directory components,
they are included. This variable is also known as
*. This local variable may be used in sources on dependency
lines, because it exapnds to the proper value for
each target on the line. Outside suffix rules, this variable
evaluates to the current target name. The name of
the target; also known as @. This local variable may be
used in sources on dependency lines, because it expands to
the proper value for each target on the line.
The shorter forms>, <, *, ?, %, ! and @ are permitted for
backward compatibility but are not recommended. For example:
$@ == $(@) == ${@} == $(.TARGET) == ${.TARGET}
You can also use these local variables appended with D or
F, where Indicates that the local variable applies to the
directory part of the name. This is the pathname prefix
without a trailing / (slash). For current directories, D
is a (period) Indicates that the local variable applies to
the filename part of the name
The $? local variable can represent a list of sources.
When used with D or F, the local variable can represent a
list of directory and filename parts, respectively.
In addition, make sets or knows about the following variables:
A single dollar sign ($); that is, $$ expands to a
single dollar sign.
The make command also knows about the following environment
variables: Determines the locale to use for the
locale categories when both LC_ALL and the corresponding
environment variable (beginning with LC_) do not specify a
locale. Determines the locale to be used to override any
values for locale categories specified by the setting of
LANG or any other LC_ environment variable. Determines
the locale for the interpretation of sequences of bytes of
text data as characters; for example, single- versus
multi-byte characters in arguments. Determines the language
in which messages should be written. The environment
variable MAKEFLAGS may contain anything that may be
specified on make's command line. Anything specified on
make's command line is appended to the MAKEFLAGS variable,
which is then entered into the environment for all programs
that make executes. Note that the operation of the
-f and -p options in the MAKEFLAGS variable are undefined.
Command line options will have precedence over the -f and
-p options in this variable.
A facility is provided to read the contents of another
file while within a description file. The syntax of this
is as follows: include file
include $(file)
When make encounters a line beginning with the word
include followed by another word that is the name of a
makefile (for example, include depend), make attempts to
open that file and process its contents as if the contents
appeared where the include line occurs. This behavior
occurs only if the first noncomment line of the first
makefile read by make is not the target; otherwise, a
syntax error occurs. An alternative, and more portable,
method is to invoke make with two or more instances of the
-f makefile. For example: $ make -f makefile1 -f makefile2
Variables Modifiers [Toc] [Back]
Variable expansion may be modified to select or modify
each word of the variable (where a ``word'' is white-space
delimited sequence of characters). The general format of
a variable expansion is as follows: SYNTAX: ${variable[:modifier[:...]]}
Each modifier begins with a colon and one of the following
special characters. The colon may be escaped with a backslash
(\). Replaces each word in the variable with its
suffix. Replaces each word in the variable with everything
but the last component. Select only those words
that match the rest of the modifier. The standard shell
wildcard characters (*, ?, and []) may be used. The wildcard
characters may be escaped with a backslash (\). This
is identical to M, but selects all words which do not
match the rest of the modifier. Replaces each word in the
variable with everything but its suffix. Modify the first
occurrence of old_pattern in each word to be replaced with
new_pattern. If a g is appended to the last slash of the
pattern, all occurrences in each word are replaced. If
old_pattern begins with a carat (^), old_pattern is
anchored at the beginning of each word. If old_pattern
ends with a dollar sign ($), it is anchored at the end of
each word. Inside new_string, an ampersand (&) is replaced
by old_pattern. Any character may be used as a delimiter
for the parts of the modifier string. The anchoring,
ampersand and delimiter characters may be escaped with a
backslash (\).
Pattern matching % character in
old_string=new_string variable substitution.
Currently, make support variable substitution
:${variable:old_string=new_string}. In addition to
this, if old_string or new_string does not contain
the pattern matching character % then it is assumed
that they are anchored at the end of each word, so
only suffixes or entire words may be replaced. Otherwise
% is the substring of old_string to be
replaced in new_string. Replaces each word in the
variable with its last component.
VPATH [Toc] [Back]
VPATH is a macro that you can set with a list of directory
pathnames separated by : (colons). It is used when
searching for a dependency-related file not found in the
current directory. If VPATH is defined, the directories
it names are searched. If it is not defined or is just
defined with a .\ (dot backslash), only the current directory
is searched. The default value is null. VPATH can
be used to search for: implicit prerequisites, internal
include files. This behavior occurs only if the first
noncomment line of the first makefile read by make is not
the target; otherwise this macro has no effect.
Support for VPATH command line token search with expanded
prerequisite repalcement:
Make searches every word/token on command lines that match
prerequisite filenames. If the word/token matches the
filename portion of a prerequisite, then the word/token
will be replaced with the VPATH expanded prerequisite
filename path specification.
Default Rules [Toc] [Back]
The default rules for the make command are read and processed
at command startup. They are contained in an
external file (/usr/share/mk/posix.mk). This file contains
exactly what XPG4b X/Open CAE Specification (1992)
Commands and Utilities, Issue 4 says it must contain.
To display the default rules, use the following command
from /bin/sh: $ make -p -f /dev/null
To stop make from reading and using the default rules, use
the following command from /bin/sh: $ make -r
Configuration File Support [Toc] [Back]
The configuration file Makeconf is used to alter the
default rules. This file can contain the definitions of
several macros. When make is invoked, it searches for
this configuration file. This file can contain rules that
override the default rules make uses. The make facility
searches for this file, starting in the current directory
and continuing through the build tree to its root. Some
special targets such as or targets which may need path
manipulation during parsing time may not be defined in
Makeconf file, otherwise make behavior may be undefined.
Comments [Toc] [Back]
Comments begin with a # (number sign), anywhere but in a
shell command line, and continue to the end of the line.
Environment [Toc] [Back]
The make command uses the MAKEFLAGS environment variable,
if it exists.
The make command exits with 0 (zero) on success, and
greater than or equal to 1 if an error occurred. In addition,
if the -q option was specified, make exits with 1 if
the target was not up-to-date.
Default POSIX rules for the make(1p) utility. List of
dependencies. List of dependencies. Configuration file.
List of dependencies. List of dependencies. List of
dependencies. List of dependencies. make(1p) POSIX make
command.
Commands: make(1), make(1u)
make(1p)
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