NAME    [Toc]    [Back]

     uperf - performance counters driver

SYNOPSIS    [Toc]    [Back]

     uperf* at ebus?
     uperf* at sbus? slot ? offset ?

DESCRIPTION    [Toc]    [Back]

     Some UltraSPARC host bridges provide performance counters on
their host
     bridges.   The  counters are a part of the system controller
chip (usc,
     dsc, or qsc).  On PCI machines the system  controller  shows
up as a device
     on  the EBUS, but on SBUS machines the system controller exists in SBUS
     space.  The uperf driver provides access to  these  counters
via ioctl(2).

IOCTLS    [Toc]    [Back]

     All  of  the  ioctl calls supported by the uperf driver take
the following
     structure as an argument:

           struct uperf_io {
                   int cnt_flags;
                   int cnt_src0;
                   int cnt_src1;
                   u_int32_t cnt_val0;
                   u_int32_t cnt_val1;
           };

     The cnt_flags field specifies which counters are being operated on and is
     a bit mask of UPERF_CNT0 and/or UPERF_CNT1.

     The  cnt_src0 and cnt_src1 fields specify the source for the
counter.  Not
     all counters support monitoring all sources  and  specifying
an invalid
     source  for  a  counter  to monitor will result in an error.
The sources are
     specified below:

           UPERFSRC_SYSCK    system clock ticks
           UPERFSRC_PRALL    all p-requests
           UPERFSRC_PRP0     p-requests from processor 0
           UPERFSRC_PRU2S    p-requests from the U2S
           UPERFSRC_UPA128   cycles UPA 128 bit data is busy
           UPERFSRC_UPA64    cycles UPA 64 bit data is busy
           UPERFSRC_PIOS     cycles stalled during PIO
           UPERFSRC_MEMRI    memory requests issued
           UPERFSRC_MCBUSY   cycles memory controller is busy
           UPERFSRC_PXSH     stall cycles due to pending transaction
                                            scoreboard hit
           UPERFSRC_P0CWMR    coherent  write miss requests, processor 0
           UPERFSRC_P1CWMR   coherent write miss  requests,  processor 1
           UPERFSRC_CIT      coherent intervention transactions
           UPERFSRC_U2SDAT   data transactions on U2S
           UPERFSRC_CRXI     coherent read transactions issued
           UPERFSRC_RDP0     read requests, processor 0
           UPERFSRC_P0CRMR   coherent read misses, processor 0
           UPERFSRC_P0PIO    PIO accesses, processor 0
           UPERFSRC_MEMRC    memory requests completed
           UPERFSRC_P1RR     read requests, processor 1
           UPERFSRC_CRMP1    coherent read misses, processor 1
           UPERFSRC_PIOP1    PIO accesses, processor 1
           UPERFSRC_CWXI     coherent write transactions issued
           UPERFSRC_RP0      read requests, processor 0
           UPERFSRC_SDVRA     streaming  DVMA read transfers, PCI
bus A
           UPERFSRC_SDVWA    streaming DVMA write transfers,  PCI
bus A
           UPERFSRC_CDVRA     consistent DVMA read transfers, PCI
bus A
           UPERFSRC_CDVWA    consistent DVMA write transfers, PCI
bus A
           UPERFSRC_SBMA     streaming buffer misses, PCI bus A
           UPERFSRC_DVA      DVMA cycles, PCI bus A
           UPERFSRC_DVWA      words transferred via DVMA, PCI bus
A
           UPERFSRC_PIOA     cycles consumed by PIO, bus A
           UPERFSRC_SDVRB    streaming DVMA read  transfers,  PCI
bus B
           UPERFSRC_SDVWB     streaming DVMA write transfers, PCI
bus B
           UPERFSRC_CDVRB    consistent DVMA read transfers,  PCI
bus B
           UPERFSRC_CDVWB    consistent DVMA write transfers, PCI
bus B
           UPERFSRC_SBMB     streaming buffer misses, PCI bus B
           UPERFSRC_DVB      DVMA cycles, PCI bus B
           UPERFSRC_DVWB     words transferred via DVMA, PCI  bus
B
           UPERFSRC_PIOB     cycles consumed by PIO, bus B
           UPERFSRC_TLBMISS  TLB misses
           UPERFSRC_NINTRS   interrupts
           UPERFSRC_INACK    interrupt NACKS on UPA
           UPERFSRC_PIOR     PIO read transfers
           UPERFSRC_PIOW     PIO write transfers
           UPERFSRC_MERGE    merge buffer transactions
           UPERFSRC_TBLA      DMA  requests retried due to tablewalks, PCI bus A
           UPERFSRC_STCA     DMA requests retries due to STC, PCI
bus A
           UPERFSRC_TBLB      DMA  requests retries due to tablewalks, PCI bus B
           UPERFSRC_STCB     DMA requests retries due to STC, PCI
bus B

     The cnt_val0 and cnt_val1 contain the values fetched for the
counters.
     Software using this interface should be prepared  to  handle
the counters
     rolling over.

     The  uperf  device responds to the following ioctl(2) calls,
which are defined
 in <dev/sun/uperfio.h>.

     UPIO_GCNTSRC  (struct  uperf_io)  Retrieve  the  source  the
counters are monitoring.
   The  cnt_flags  is  a  bit mask for
which of the
                   counters is to be fetched.  The result is  returned in
                   cnt_src0 and/or cnt_src1.

     UPIO_SCNTSRC   (struct uperf_io) Set the source the counters
should monitor.
  This call also clears the current  value
of the counters
  that  are  set.   The cnt_flags is a bit
mask for which
                   of the counters is to be  set.   The  cnt_src0
and/or cnt_src1
                   fields  specify  the  source to be set for the
respective
                   counter.

     UPIO_CLRCNT   (struct uperf_io) Clear the counters specified
in
                   cnt_flags.

     UPIO_GETCNT    (struct  uperf_io) Retrieve the value for the
counters specified
 in cnt_flags.  The values  are  returned
in cnt_val0
                   and/or cnt_val1.

SEE ALSO    [Toc]    [Back]

     ioctl(2), ebus(4), intro(4), sbus(4)

HISTORY    [Toc]    [Back]

     The uperf driver was first supported in OpenBSD 3.1.

AUTHORS    [Toc]    [Back]

     The  driver was written by Jason Wright <[email protected]>.

OpenBSD     3.6                        January      30,      2002